Optical receiver techniques for integrated photonic links

Integrated photonics has emerged as an I/O technology set to disrupt the communication fabric of many-core computer systems. The optical technology uses wavelength-division-multiplexing and a high degree of integration in order to surpass electrical I/O in both throughput and energy by more than an order of magnitude. However, integrated photonic systems need to be properly designed in order to reach their full potential, and electronic design techniques need to be updated to take full advantage of tight integration with photonics. This thesis explores the engineering of integrated photonics systems, focusing on optical data receiver design and techniques. We develop a representation of a photonic communication system based on circuit and device models, and perform a system-level optimization to find the optimal operating point for each of the components. This operating point sets the specification for the receiver circuits developed. An equivalent model of the receiver is used to develop a host of split-photodiode topologies that enable new ways to implement double-data-rate and decision-feedback-equalization operation. The receivers are fabricated as part of an integrated photonic test platform, and the measurements are detailed. This work presents the first-ever monolithically-integrated optical receiver with pA-sensitivity in a zero-foundry-change, commercial SOI CMOS logic process, and the first-ever monolithically-integrated optical receiver in a bulk CMOS memory process as part of a 9x5Gb/s DWDM receiver bank. Thesis Supervisor: Vladimir Stojanovid